2 research outputs found
HashCore: Proof-of-Work Functions for General Purpose Processors
Over the past five years, the rewards associated with mining Proof-of-Work
blockchains have increased substantially. As a result, miners are heavily
incentivized to design and utilize Application Specific Integrated Circuits
(ASICs) that can compute hashes far more efficiently than existing general
purpose hardware. Currently, it is difficult for most users to purchase and
operate ASICs due to pricing and availability constraints, resulting in a
relatively small number of miners with respect to total user base for most
popular cryptocurrencies. In this work, we aim to invert the problem of ASIC
development by constructing a Proof-of-Work function for which an existing
general purpose processor (GPP, such as an x86 IC) is already an optimized
ASIC. In doing so, we will ensure that any would-be miner either already owns
an ASIC for the Proof-of-Work system they wish to participate in or can attain
one at a competitive price with relative ease. In order to achieve this, we
present HashCore, a Proof-of-Work function composed of "widgets" generated
pseudo-randomly at runtime that each execute a sequence of general purpose
processor instructions designed to stress the computational resources of such a
GPP. The widgets will be modeled after workloads that GPPs have been optimized
for, for example, the SPEC CPU 2017 benchmark suite for x86 ICs, in a technique
we refer to as inverted benchmarking. We provide a proof that HashCore is
collision-resistant regardless of how the widgets are implemented. We observe
that GPP designers/developers essentially create an ASIC for benchmarks such as
SPEC CPU 2017. By modeling HashCore after such benchmarks, we create a
Proof-of-Work function that can be run most efficiently on a GPP, resulting in
a more accessible, competitive, and balanced mining market
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Improving proxy accuracy : experiments with branch, memory, and over time behavior
As computers and the workloads they run have grown in size and complexity, it has become difficult to test the performance and power of future products under design. These products (future processor and memory systems) are often designed on simulators that are orders of magnitude slower than the final product. Full-fledged workloads are simply too long and complex to run on cycle accurate simulators. For this reason, industry and academia have developed simulation region methodologies, such as SimPoint, that identify the most representative regions of the workloads. Most architecture researchers use dominant SimPoints in their architectural design explorations. However, in order to study runtime adaptive techniques for performance and power/energy management, it is important to capture the over time phase behavior of workloads. SimPoint has been demonstrated to capture average behavior accurately, but it is not known whether a sequence of SimPoints can capture the over time program phase behavior. To explore this, we propose SimTrace, an ordered sequence of SimPoints. We then use existing similarity techniques for time series to analyze and evaluate the accuracy of SimTrace to capture the over time phase behavior of the original workload. Using SPEC CPU 2017 benchmarks as a case study, we observe good accuracy for SimTrace: with less than 5% performance error (Instructions Per Cycle) for four time-series metrics.
However, for techniques like SimTrace to work in real world environments techniques are needed to create simple executables for these SimPoints. One promising technique is program approximations which extract key characteristics from a workload. However, the techniques for creating Synthetic proxies are insufficient to handle current micro-architecture structures and the more complex workloads being run. Additionally, generating proxies has up to this point required expert tuning in order to perform well. This report covers some development on these proxies to increase automation and to extend the branch and memory models. Experimental results show improvements of up to 10x in accuracy for memory and branch behavior.Electrical and Computer Engineerin